The semiconductor industry’s highest performance, most reliable and scalable design data management platform

Streamlines the building of complex IP and releasing SoCs to fab

Ensures the correct data is quickly and efficiently delivered to the right user

10-100x faster performance

Scales from small teams to enterprises with thousands of users

Single source of truth to design and tapeout with confidence

Ultimate IP and SOC environment

High performance configuration management

Adaptable analog and digital workflows
Tight integration with custom design tools including Cadence Virtuoso, Synopsys Custom Compiler

IP Management at scale

Flexible IP packaging with full traceability
Hierarchical assemblies for producer-consumer handoffs
‍Powerful user interface with intuitive search

Configurable IP search and IP data sheets
‍1M+ design components in repository

Global multi-site reliability

Thousands of users working 24x7 across global design centers
Every design change captured with atomic change lists each component has its own change audit
Fully automated release and derivative creation and tracking
Tracing extends to additional services: bug tracking, requirements management, PLM

GDP XL Online Demos

CHAPTER 1

IC Manage GDP XL Introduction

CHAPTER 2

IC Manage GDP XL Repository Organization

CHAPTER 3

IC Manage GDP XL IP Create, Configure and Release

CHAPTER 4

IC Manage GDP-XL SoC Assembly, Release, Tapeout

CHAPTER 5

IC Manage Version Control with Cadence Library Manager

CHAPTER 6

IC Manage Version Control with Synopsys Custom Compiler

Global Design Platform XL performance metrics

METRIC

GDP-XL

OTHER

FULL SOC CREATE
(2514 ELEMENTS)

20 SEC

8500 SECONDS
(2.5 HOURS)

FULL SOC LIST
(1443 ELEMENTS)

1.1 SEC

910 SECONDS
(15 MIN)

FULL REPOSITORY LIST
(100K ELEMENTS)

1.3

N/A
EXCEEDS CAPACITY

FULL REPOSITORY SEARCH
(100K ELEMENTS)

0.2 SEC

N/A
EXCEEDS CAPACITY

Global Design Platform has been a key part of our design infrastructure for over 15 years. We depend on it to support hundreds of engineers and it is essential for us to manage any number of GPU and AI SoC projects targeting multiple foundries and technologies. This allows us access to any fab and the manufacturing capacity that we need for high volume products.

Ajay Chandna

CAD Engineer